As transistor dimensions are scaled, spacers used to place silicide away from the source-drain to body junction have likewise reduced in dimension. To prevent junction leakages associated with silicide encroachment, epitaxial overfill in the S-D has been utilized to increase silicide proximity away from the junction. The structural and selectivity requirements for this overfill can result in material and electrical properties that can negatively impact device performance.
Also, different devices with varying requirements for leakage and performance can require different levels of S-D overfill. However epitaxial S-D formation is also a very complex and costly process, and hence it is desirable to minimize the variations of epitaxial growth included in a process.